Set signal high for one clock step

[slirenem]

Hi,

as in title, how to set signal to '1' for one clock time step and then go back to '0' in VHDL? It is kind of data_strobe signal.

Best regards
slir

 

[barry]

Assuming you have some trigger to start this, one way of doing this (FSM):
if clk='1' and clk'event then
.
.
.
case state is
case idle =>
if trigger ='1' then
strobe<='1';
state<=s1;
else
strobe<='0';
state<=idle;
end if;
case s1 =>
strobe<='0';
if trigger='0' then
state<=idle;
else
state<=s1;
end if;
end case;

 

[TrickyDicky]

Whats the requirement? '1' for 1 clock after reset? does it have a trigger?

A state machine may be appropriate depending on your requirements, but may be overkill.

 

[slirenem]

It is to inform UART controller to send prepared data. I set it to '1' when it is one of FSM state but don't want that UART repeat sending so after inform it I would like to set this signal to '0'.

 

[TrickyDicky]

just have a state that lasts for 1 clock cycle only

 

[slirenem]

Aaa, and when others set to '0'. Thanks a lot