Sequential Circuit

[Basit Mehmood]

What happened if we use blocking assignment in sequential circuit like flip-flop?
I mean is following code correct or not?

---

Code Verilog - [expand]
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module dff (q, qn, d, clk);
   input d, clk;
   output q, qn;
   reg q, qn;
   always @(posedge clk)
      begin
         q = d;
         qn = ~d;
      end
endmodule

---

 

[ThisIsNotSam]

conceptually, it is wrong.
depending on the synthesis tool, it might synthesize correctly.

 

[FvM]

1. What do you want to achieve? Just playing around?
There's a reason, why design rules say use non-blocking in clocked always block and blocking in combinational. For a comprehensive explanation, read this classical paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf

2. In this special case, non-blocking assignments make no difference. That's because the assigned variable q and qn aren't appearing on RHS of other expressions below the assignment.

3. Sometimes you want intermediate combinational results assigned to a variable inside a clocked always block. In this case, blocking assignments may be used intentionally.