Scanning in the design

[sun_ray]

How scan chains are inserted in the design? How to decide about scan chain length and number of scan chains? When is scan chain inserted in the design? How does scan testing happens?

What is compressing and masking in brief?

 

[rca]

The scan chains are generally inserted after the first synthesis.
The number of scan chain is related of the tester capacity.
The basic scan chain (without test compressor) could be inserted by th synthesis tool, like dc, RC.
The atpg loads a value in each flops in the scan chains and after execute a capture cycle to capture the logic functionality and shift the result to check the result is as expected.

 

[sun_ray]

rca
What is compressing and masking?

Can you please explain "The atpg loads a value in each flops in the scan chains and after execute a capture cycle to capture the logic functionality and shift the result to check the result is as expected." in more detail?

What are dft rule violations for registers? What type of violations are they?

---------- Post added at 11:29 ---------- Previous post was at 11:27 ----------

 

[rca]

during the scan shift phase, the flop are loaded with a knowned value and the previous value is shifted-out to check the previous capture.
this is following with a capture phase, to capture the logic functionality and so on...

 

[dbshailesh]

#1. SCAN Chain is a Serail Shift register structure...where in you can pump in/out data from Chip pins, and with scan_enable control you can bring the data into FLOP from D path instaed for SI path, i.e. known as Capture cycle
#2. Compression s is nothing but comressing the data pumped into/out of many registers and masking is if we see any X on a compressor chain, we do mask that chain/flop observation
#3. For more details refer any ATPG Cycle in the net for MUX based scan structure

 

[ranger01]

How to decide about scan chain length and number of scan chains? When is scan chain inserted in the design? How does scan testing happens?

What is compressing and masking in brief?

number of scan chain depends on various factors like, number of clock domains, tester memory, testing time and tester supported channels for scan,

scan is inserted once you define scan architecture and ask DFT tool to insert scan, in the synthesis flow.

as rca mentioned, scan flops are loaded with pre-defined values(decided by the ATPG patterns) and apply capture pulse to record the response of internal combo logic and shift out the recorded values and cross check with the expected values. This is the basic operation of pattern simulation

scan compression -> add a de compressor and a compressor in the design, which helps to reduce the number of patterns by preserving the coverage. due to the added structures the design will be prone to propagate x, which reduces the coverage. So x masking circuitry will be used to block this.

Hope this helps!