sampling in Cadence and fft in Matlab

[tyd]

cadence to matlab fft

I need help for my pipelined ADC. I sampled the output and used matlab to get fft. Using the program in this forum, I calculate SNR,THD,etc. But I have problem during this procedure. I sampled the single sin wave, using Matlab code, SNR is just about 100dB. But when I tried to sampled the ouput from ideal DAC(I tested the example in Baker's book(mixed signal circuit design), on page 38), I got SNR just 30dB.But for 8-bit ADC, it is supposed to be greater than 40dB. I used the method called coherent sampling on maximum web site to find optimum test tone, I tried the way I found this this web site.I tried to change the sampling frequency and input frequency,But it always 30dB. I used the same way to test my first stage ouput of pipelined ADC, SNR is just about 20dB.I check the input and output from DAC,they are very close.The difference is the second is sampled. But nothing changes.I can't get expected SNR.I hope I can get suggestions.Thanks.

 

[svensl]

coherent fft cadence

I cannot comment on your matlab code, but I can give a few suggestions.
First, try to choose an input frequency that is a prime number. For example, 13/128 Mhz for an 128 FFT. In this way you make sure all of the DAC/ADC codes get exercised. Make sure you are taking the numbers of samples to be a power of two.
Give the circuit a little time to start up before taking samples, like 100ns.
When you take the samples form cadence consider strobing them.

svensl

 

[ocarnu]

fft hspice delmax time

You should also make sure that the value of the output is computed exactly in the point you want to save (not calculated trough interpolation). This can make large difference in SNR. Also, the accuracy parameters you set make difference.

 

[tyd]

cadence sinüs fft adc

Thank you so much for your help. That problem makes me crazy.But I will try again. But I still don't understand teh second answer. The output from first stage is supposed to be sampled sin wave, do you mean I should sample teh data in hold mode?What do you mean accuracy parameter?Could you give mea an example?

Thank you so much for your time and your help.

 

[ocarnu]

cadence matlab fft

Yes, you should sample the data in the hold mode at the end, after complete settling, if you want to sample the output of the analog part (op amps). If you sample the digital data (after comparators), it doens't realyy matter.
For accuracy, there are more parametrs, what I remeber now is delmax which gives the maximum step.
Check this out:
**broken link removed**

 

[mr_chip]

fft matlab cadence

I think you're sampling the digital data at the output of the pipeline of the ADC, so settling is not a problem. Just make sure that the digital values are exactly vdd & vss (or 1 and 0) - use rounding if necessary.

 

[tyd]

thd delmax hspice

Thank you very much for you help!I got the correct result for ideal case.But for real ADC, It seems that settling is still a problem.The difference between the output of first stage and second stage is one and half phase!

Added after 2 hours 13 minutes:

I still have one question.If I sampled the digital data, How to get fft spectrum from that data.Right nor,I used ideal DAC at the end of ADC and chenged that digital data to analog data.

Thank you so much for yoru help.

 

[sunking]

for digital data, you can download it and anaysis by fft of matlab.
pay attention to that you should have integral period of the signal or you have to added the window

 

[tyd]

Thank you for your help.I am still a little confusing about this.I need to use matlab to convert digital output to analog output?It seems that it is not easy to do that.I need 1024 "if statement" for 10 bit ADC.I am really don't know how to do fft using digital signal.Thank you so much for yoru help.