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sample and hold using rail to rail for ADC..

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maori

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im a newbiee...here i attach the circuit of my study

1)i also attach a little bit that i understand now...but i still not sure if it right or wrong
i hope some one can tell me if i wrong.

2) i want to know more about the complementary differential pair that been used as
an input in this circuit.and the second stage operation
I hope some one can tell me in real detail.

3)the output of sample and hold is as second figure that i attach here.can some one
tell me how to explain the result to my study of ADC.how i want to explain from the
result is it good for adc or not.

im still studying...but alot of paper that i read in internet confusing me asspecially about the complementary differential pair input...i hope there is some one can explain it better.
 

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