sample and hold for adc

[mubi17]

do i need seperate sample and hold for different parallel stages of 6 bit flash adc using 0.18u or only one S/H can take load of all stages

 

[A.Anand Srinivasan]

no.... one sample and hold is enough provided you control the droop properly....

 

[batistuta]

in flash architecture ADC do not need S/H circuit.

 

[A.Anand Srinivasan]

how do you say we dont need an S/H circuit... there is finite propogation delay in the signal being seen by each of the comparator down the array of comparators used....

in 6 bit obviously there are 63 comparators and the resistive ladder plus the parasitic capacitance would cause errors if the input signal is varying fast....