Running more than one vhdl codes in fga at a same time

[nytman]

Dear sir/madam,

i was trying to process more than one vhdl code's(means its bit file) in vertix 5 fpga at a same time, but unable to do so, can any one help me and suggest me how could i approach.
Waiting for reply.

 

[Sckoarn]

nytman,
Sounds to me like you need to wrap all the VHDL code into a single entity. You can only load one bit file into an FPGA at a time.

Hope that helps
Sckoarn

 

[phoenixpavan]

Yep,

you can dump a single bit file onto a specific fpga board.If you want to have two vhdl codes to be used for dumping...then you should write a top entity for these two designs and then generate a bit file to target on a FPGA

 

[nytman]

Thanku Sckoarn and Phoenixpavan.....u both make my doubt clear.......and one more question i have....what about DSP48E in Vertix5....i think we may use it for running things parallely.....if yes then how??
Thank you in advance....waiting for your reply.

 

[phoenixpavan]

Hi nytman..

I think the board in question can support parallel connectivity...why don't you please check with the documentation of the board once..

 

[sunjianhuigou]

Yep,

you can dump a single bit file onto a specific fpga board.If you want to have two vhdl codes to be used for dumping...then you should write a top entity for these two designs and then generate a bit file to target on a FPGA

i remember can setting using the ISE tool,configure the download mode, configure downloading sram connected serially :{sram(.sof)}-{sram.sof}-{sram.sof} .