Result difference from schematic and layout simulation for a regualtor

[florescent]

Result difference from schematic and layout simulation for a regulator

Dear all

I have spent enough painful hours and days to figure what has gone wrong in my design.

I attach all files (schematic, layout, and extracted). No problems and no errors with DRC and LVS.

The CP_in is the input voltage to the regulator. It can go up to 14V which is the maximum as the gate oxide breakdown voltage. It does not matter what the level of CP_in is. The output voltage of the regulator (VDD_out) in extracted is always higher than one in schematic (at least 250mV higher). For example, when CP_in is set to 10 DCV, the VDD_out of the extracted is 2.788 V. However, with the same setup, the schematic simulation gives me 2.524 V

I double triple checked and compared the parameters of the components from both schematic and extracted. They are all same and fine.

What have I done wrong?

Please take my bow and in advance to whom address me the correction(s)

Thank you very much

 

[erikl]

Re: Result difference from schematic and layout simulation for a regulator

What have I done wrong?

Only thing I can imagine is that your bulk taps (substrate & nwell taps) in most cases are very far from their MOSFETs, which could result in some voltage drop between source & bulk (there's always some leakage between channel & bulk), so changing slightly its Id characteristic. This is especially decisive for the 3 series output pMOSFETs to GND, which generate their own nwell potential levels.

You might object that the source and bulk tap are shorted by metal -- this is true -- nevertheless there could be a leakage generated voltage difference between source and bulk at the proper source position which forward biases the bulk.

Usually, DRC rules prohibit too much distance between the active area of a MOSFET and its bulk tap -- generally this distance should be in the order of W -- in your case it's 3..4 * W for P{136,137,140}. See your DRC rules if this isn't checked?

Just a possibility, I'm definitely not sure! You could try and check by inserting a reasonable resistor between source and bulk of those 3 pMOSFETs.

 

[florescent]

Re: Result difference from schematic and layout simulation for a regulator

Dear erikl

Based on your theory, I inspected on the PMOS's at the output. The minimum channel length for any MOSFET in this regulator is 1.95um. However, I used 0.6um for the four PMOS's at the output. As soon as I changed them to 1.95um, the results became the same. But why?

 

[erikl]

Re: Result difference from schematic and layout simulation for a regulator

As soon as I changed them to 1.95um, the results became the same. But why?

The 3 diode-connected PMOSFETs are well in saturation, so I think their W/L ratio isn't too critical.

Why do you feed back from P136's drain/gate (net114) and not directly from VDD_out ?
Do you need VDD_out to be by Vth larger than your Vref (net98)?

 

[florescent]

Re: Result difference from schematic and layout simulation for a regulator

Dear erikl

When I changed the CP_in there is a difference again between the schematic and extracted. Changing the channel length on the pMOS's did not help due the the deep saturation

I moved the bulk tabs also closest possible the their channels, but it did not change at all.

It is very weird.

 

[erikl]

Re: Result difference from schematic and layout simulation for a regulator

Does your Vref (net98) change between pre- & postLayout simulation?

Did you make sure that the start-up FETs P43 & P48 are fully off (|Id| < 1pA) after the start-up period?

Compare all pre- & postLayout node voltages to possibly find a clue for the deviation!

 

[florescent]

Dear erikl

When I connect the right side of the input opamp to the output, I couldn't get enough regulated voltage as 2.5.

The node voltage at the top reference (which goes to the opmap) is 1.675/1.856, where schematic/extracted respectively.
The node voltage at the bottom reference (which goes to the opamp biasing is 0.73/0.805
The input voltage to the other side of the opamp (which goes to the top Gate of the three pMOS series) is 1.678/1.859
Basically, all numbers are different between the schematic and extracted.
Isn't it because of too narrow paths with relatively high power input? What if I increase width of all connections and path at least double or triple?

Thank you

 

[florescent]

The pdf file shows the output comparison. This is what has happening

Even though I increased all the paths at least three times, it gives me the same results
I'm pulling my hairs

 

[erikl]

Re: Result difference from schematic and layout simulation for a regulator

Did you make sure that the start-up FETs P43 & P48 are fully off (|Id| < 1pA) after the start-up period?

Pre- & postLayout voltages at net 131 (and CP_in)?

Or just try and deactivate the 2 MOSFETs in order to make sure that they really are off.

 

[florescent]

Dear erikl

The two pMOS's (p43 and p48) which are the starting up circuit turn off completely. The id from both pre&post layout are zero or very close to zero

The voltage at "net 131" = "CP_in". For example, when CP_in is supplied with 10V. The net 131 gets 10V from both pre&post layout

Thank you

 

[erikl]

Ok. Then I suggest to compare the 2 netlists visually. Depending on the setting of the LVS rules, LVS comparison can be rather tolerant concerning deviations in the R-,W- & L-values (in the order of several %), but deviations in such order could perhaps be responsible for those voltage differences. I'd start to compare the values of R3 and of the 6 transistors above -- because you already see voltage differences on the nets 98 & 106 .

 

[florescent]

Dear erikl

Thank you for your recommendations all the time. It really helped me figure out.

The problem is still in the air, but I'm very close to the conclusion. As you see my customized layouts, I always use multiplier for big MOSFET's. When I got rid of all multipliers, especially the reference MOSFET's, the results between the sch and post-layout were matched. They are the same W/L (overall) even though I use multipliers. That's why I got no size mismatch error on LVS. But why?. Why no-multiplier does work?

This is another example how the multiplier affects the circuit simulation

I used all the multipliers as I used to do. But only mosfet I changed the multiplier was N45, the one connected to the resistor. This is the result

Multiplier VDD_out
1 2.893
2 2.883
6 2.838
10 2.77

Of course, when I used a multiplier, I changed the unit width so that the total W/L remained 45/1.95 always.

Thank you

 

[erikl]

But why?. Why no-multiplier does work?

There could be 2 different reasons:

1. only if you use automatically generated layouts of multiple-finger MOSFETs: Perhaps the layout algorithm doesn't follow exactly your requirements, or

2. the extraction rules aren't good enough to reproduce the effective W & L values: multiple-finger transistors have more complex geometries, i.e. are more difficult to be extracted

In both cases you should be able to find out differences if you compare the respective MOSFETs in the netlists manually/visually.