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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 if rising_edge(clock) then data_valid<= '0'; case state when sniffing=> if data_byte = (others=>'0') then mux_sel = '1'; else mux_sel = '0'; mux_data_in0 <= data_byte; data_valid <= '1'; state <= tx; end if; when tx => if rx = '1' then state <= sniffing; end if; end case; ... .. if data_valid = '1' then data_in <= data_byte; rx <= '1'; end if;