Reliability question for a casode 3.3V buffer using 1.8V MOS.

[dr_kca]

Relibility question for a casode 3.3V buffer using 1.8V MOS.

Hello,


In a 3.3V cascode output buffer design using 1.8V transistors (two cascoded PMOS and two cascoded NMOS as shown in the figure below), the cascode configuration is used on order to keep |Vgs| of MOS devices within the allowed voltage range. I was thinking if the same constraint is also valid for Vds? The documentation that I have does not really specify anything for Vds in terms of reliabilty, it only says that if this voltage is greater than 1.98V ( 1.8+10%) it is out of specification for SOA analysis. Is it wrong to assume that the Vds (since no oxide) limitation is more relaxed, and MOS can tolerate a few hundreds of milivolts of over-voltage between its drain and source for a short interval during a switching activity due to the short-circuit current when both P and N is ON ? This latter assumption is it a problem for PBTI/NBTI phenomena?

PMOS have a slower switching response than NMOS due a fail-safe structure, which is not shown in the figure below. This structure causes a short-circuit current that lasts longer and I was wondering until which point I should keep optimizing my buffer design.

thank you very much,

 

[dick_freebird]

Re: Relibility question for a casode 3.3V buffer using 1.8V MOS.

It's more common in my experience (which however does
not extend below 100nm) that Vds is the more common
supply voltage limiter, than Vgs when it comes to reliability
wearout mechanisms. Cascodes address Vds and to some
extent Vgs, and in the "guard" devices Vgs is reversing.

It -is- wrong to assume Vgs more sensitive than Vds,
you are looking at two different device aspects / features
(hot carrier for Vds, oxide wearout for Vgs) and both are
device / process architecture trades. But it's the
-assuming- that is wrong, even if the facts in one case
come out as assumed.

 

[dr_kca]

Re: Relibility question for a casode 3.3V buffer using 1.8V MOS.

thank you for your answer,
It is very helpful since now I see better where my reasoning was wrong.

 

[khaled2k]

In my experience, the foundry will never state the maximum voltage stress. In power amplifier, the drain to source voltage usually reaches 2 Vdd (for a single transistor). As a rule of thumb, you can say that Vds can reach (2 *1.8V) and Vgs (1.5 * 1.8V) for a short time.
The realiability has no clear definition in literatures and in some papers maximum voltage stress, in others maximum voltage stress for a certain time.