singu31
Newbie level 5
low vt high vt
Hi,
I went through a couple of papers on Multiple Vt CMOS structures for low power design. In all of these they say that scaling down supply voltage reduces power consumption as
Power α (VDD)^2.
But as we scale down supply voltage we also have to scale down Vt.
I dont understand exactly why the leakage current increases as we scale down Vt? Why do high Vt transistors have lesser leakage than Low Vt transistors?
Please clarify.
Thanks
Singaravelan
Hi,
I went through a couple of papers on Multiple Vt CMOS structures for low power design. In all of these they say that scaling down supply voltage reduces power consumption as
Power α (VDD)^2.
But as we scale down supply voltage we also have to scale down Vt.
I dont understand exactly why the leakage current increases as we scale down Vt? Why do high Vt transistors have lesser leakage than Low Vt transistors?
Please clarify.
Thanks
Singaravelan