Bharath Kumar
Newbie level 1
Hi everyone,
I have been put in a project of doing gate level simulation of an ASIC.
Please some one help me with my question.Will there be any openings for gate level simulation or Should i learn functional verification also........
With regards,
M.Bharath
I have been put in a project of doing gate level simulation of an ASIC.
Please some one help me with my question.Will there be any openings for gate level simulation or Should i learn functional verification also........
With regards,
M.Bharath