regarding the parallelism in vivado HLS

[sai_shashi]

HI there,

I have an algorithm which has many for loops and i am using vivado HLS for pipeling the algorithm and run on FPGA. How will i know where exactly to parallelize?
Can i PIPELINE all the for loops.?
Will the coordination of the for loops be taken care?

Thank you in advance..

 

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If the for loops are to do something in sequence, e.g. a shift register producing a serial bit stream, then you can't make it parallel as making a shift register parallel will mean it no longer functions as a shift register.

So without a lot more information, only you can decide if something can be made parallel or not.