Regarding the different data width between 2 DSP IP cores- FPGA

[Maitry07]

Hello support team,

I am using 2 different ready FPGA IP cores with different data widths and I want to interface the 1st IP output data continuously with the 2nd IP input. Details as below.

1. Interfacing IP core - 1st IP core, which has a data width of 64 bits with a clock frequency of 15.36 MHz ( 0.0651041 usec) , that means for the single sample(16 bits)- the clock period is 0.0162760 usec ( 0.0162760 x 4 = 0.0651041 usec ) and it is providing continuous data.
2. Arithmetic IP core- 2nd IP core, which has a data width of 16 bits with variable clock frequency selection. So, in order to provide all samples from interfacing IP core output to arithmatic IP core input, If I select the clock frequency of the arithmetic core as 61.44 MHz. then it would be possible for this core to take 16 bits( 1 sample) in 0.0162760 usec.
So, as my interface IP core is providing 0-63 bits ( 0-15, 16-32, 33-48, 49-63 bits ) and my arithmetic core is taking 16(0-15) bits as input width. what should be the suitable option( may be loop) so that arithmetic core can take input in such a manner (0-15, 16-32, 33-48, 49-63 and then again 0-15, 16-32 ....)

 

[KlausST]

Hi,

If I understand correctly, then
one core is 64 bits output --> the other is 16 bits inputs.

My questions are:
* do you need 64 bits resolution?
* ( if not, is 16 bits sufficient? If so, just choose the correct 16 bits from the 64 bits to feed the second core. Done)
* are both cores running from the same system clock? Or do you need to overcome a clock boundary?

Klaus

 

[Maitry07]

Hi,
Answers
1. Yes, actually 64 bits has 4 continuous 16 bits samples ( sample0=16 bit, sample1=16 bit, sample2=16 bit, sample3=16 bit) so I need to further provide all these samples in a serial manner, which is like sample0, sample1, sample2, sample3. ...., sampleN.
2. 1st core is running with 15.36 MHz ( i.e ( 0.0651041 usec)) and for the 2nd core, I have provided 61.44 MHz clock( 0.0162760 usec)- because it has the data width of 16 bits. - which is the (0.0651041 usec /4 ) = clock period of single sample (16 bits ) from the 1st core.

 

[FvM]

Running the arithmetic unit at exact fourfold rate may work, but it's a rather inflexible solution. The regular method would be to run it at a higher clock frequency and use a streaming interface with handshake.

 

[Maitry07]

Ok,
I got your point regarding the use of arithmatic core at 61.44 MHz clock frequency which is multiple of 4 for 15.36 MHz. but could you please more elaborate for streaming interface with handshake?

--- Updated Dec 20, 2022 ---

Actually I am running the arithematic core with 61.44 MHz but how to unpack the 1st core (61 bits data) into 4 samples ( 16 bits- sample0, 16 bits - sample1, 16 bits- sample2, 16 bits- sample3)? for this data unpacking which should be the suitable method?