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Read Margin violation of RAm

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neetinsingh

neetinsingh

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Hi

I am doing top level MBIST pattern generation and simulation for a modlue . While pattern simulation i am gettin Read margine violation for the RAM but my simulation is passing. I think it might be due to the clock frequency going in to the RAM.

I want to know what is the effect of this violation, will it cause a problem in tester while testing the chip.

also give some way too debug this issue.

Regards
Neetin
 

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