Read and writes at the same memory location

[shiny1]

Hi,

Can we read and write from the same memory location in the same clock cycle. i.e., writing at the rising edge and reading at the falling edge from the same location. Is it possible to achieve?
regards

 

[TrickyDicky]

you cannot use dual edges inside an FPGA. But most FPGA memories are duel ported, so yet you can read and write on the same clock edge on the two different ports.

 

[shiny1]

Does it mean I can access same memory location for reading and writing in the same clock cycle through different ports... Correct me if am wrong . Thank you.

 

[TrickyDicky]

yes. Read up on your selected device archiecture.

 

[j_andr]

Can we read and write from the same memory location in the same clock cycle/.../

such example is compiled by quartus without warnings and [quartus] netlist simulation
shows possibility of writing on rising edge and then reading the same location
on falling clock edge;

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Code Verilog - [expand]
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module dual_edge_ram
(
  input            clk, wr,
  input      [7:0] addr_in, addr_out,
  input      [7:0] d_in,
  output reg [7:0] d_out
);
 
reg [7:0] ram[0:255];
wire      rd_clk = ~clk;
 
 
 always @(posedge rd_clk)
   if ( wr ) ram[addr_in] <= d_in;
 
//always @(negedge clk)   
 always @(posedge rd_clk)
   d_out <= ram[addr_out];
 
endmodule

---

actually quartus inserts an inverter on the clock line and use
positive edges, like in the example, but it will accept also:
always @(negedge clk) d_out <= ram[addr_out];

j.a