Race condition problem (GateSim)

[dearjohn]

After DC Synthesis
use VCS compile gate netlist to generate fsdb
VCS hold on after run 1ms
( cannot run to $finish written by pattern)
the fsdb file size never increase
press ctrl+c
use Verdi to trace waveform cannot find any problem
( just see the clock stoped , but dont know why)
then use VCS compile RTL , it's OK
(it seems stop in some state of the state machine, but Check RTL again
it's impossible form a endless loop in this state)
May I ask
it's VCS or Verdi hold the program ?
In this situation, how to debug ????

 

[nand_gates]

Re: GateSim Probelm?

There seems to be race condition problem. Checkout simulation delta count.
You run the simulation just till 1ms where it is about to enter into hang mode,
do single stepping to find out the race!

 

[jjww110]

GateSim Probelm?

there is a bug in vcs probably

 

[power-twq]

Re: GateSim Probelm?

you can check timescale is right,

perhaps you should skew some signal to avoid race condition.

After DC Synthesis
use VCS compile gate netlist to generate fsdb
VCS hold on after run 1ms
( cannot run to $finish written by pattern)
the fsdb file size never increase
press ctrl+c
use Verdi to trace waveform cannot find any problem
( just see the clock stoped , but dont know why)
then use VCS compile RTL , it's OK
(it seems stop in some state of the state machine, but Check RTL again
it's impossible form a endless loop in this state)
May I ask
it's VCS or Verdi hold the program ?
In this situation, how to debug ????