gongdori
Full Member level 2
Hi all,
In the Xilinx V4 datasheet, there is power supply ramp time requirement (Table 6 in DS595 DC and switching characteristics).
It says that the three voltage rails should be ramp up within 0.2ms to 50 ms. (I assume 0V to the 100%?)
I wonder where this requirement comes from.
Is it needed for the silicon to power up correctly, or is it related to FPGA configuration at power up?
If it is related to FPGA configuration at power up, can it be removed, if the configuration is delayed after powering up?
Thanks,
Gongdori
In the Xilinx V4 datasheet, there is power supply ramp time requirement (Table 6 in DS595 DC and switching characteristics).
It says that the three voltage rails should be ramp up within 0.2ms to 50 ms. (I assume 0V to the 100%?)
I wonder where this requirement comes from.
Is it needed for the silicon to power up correctly, or is it related to FPGA configuration at power up?
If it is related to FPGA configuration at power up, can it be removed, if the configuration is delayed after powering up?
Thanks,
Gongdori