suria3
Full Member level 5
Hi Guys,
I have a concern on the bandgap design. I have covered the process/voltage/temperature + montecarlo simulations on both the pre layout and post layout simulations, and the result are in the
expected range with typically ~1.2V of the bandgap output voltage. The montecarlo simulations
were performed around 1000 samples run as well, where the min and max sigma deviation also
in the range of 1.15V to 1.25V (extraction simulation), which is the targeted range.
Question is, on the silicon, during the test, will the bandgap result will vary further from what we observed from the simulated range? Will it still vary beyond 1.25V, and less than 1.15V?
Thanks
Suria
I have a concern on the bandgap design. I have covered the process/voltage/temperature + montecarlo simulations on both the pre layout and post layout simulations, and the result are in the
expected range with typically ~1.2V of the bandgap output voltage. The montecarlo simulations
were performed around 1000 samples run as well, where the min and max sigma deviation also
in the range of 1.15V to 1.25V (extraction simulation), which is the targeted range.
Question is, on the silicon, during the test, will the bandgap result will vary further from what we observed from the simulated range? Will it still vary beyond 1.25V, and less than 1.15V?
Thanks
Suria