Questions about SPI interface.

[xuedashun]

I am going to design a project which uses SPI interface, which has 4 signals: SS* SCLK MISO MOSI. To my knowledge,
SS*, SCLK and MOSI are input singal and MISO is output signals. I have two questions:

1)
I am told the SPI is 25MHz. Is 25MHz too high for this SPI interface? What's the normal frequency range for SPI.

2)
In order to generate the digital output signal (MISO), I need clock signal. Is it possible to directly use SCLK to generate
this digital output signal (MISO)

Thank you!

 

[FvM]

You didn't tell, if you are designing a SPI master or slave device. The direction of signals changes respectively. MISO is e.g. master in - slave out.

Is 25MHz too high for this SPI interface?

For which SPI interface? For a FPGA or CPLD, 25 MHz isn't too high.

Typically, all SPI registers are directly clocked by SCLK. This means, that you need domain crossing techniques for a SPI slave.

 

[poluekt]

1) Typically SPI frequency 1-50 MHz, but it depends on system.
2) If system clock much faster than SCLK then you can do over-sample using system clock, it does design more complicated.

 

[FvM]

If system clock much faster than SCLK then you can do over-sample using system clock, it does design more complicated.

I think, the design becomes easier in terms of timing closure between SPI interface and rest of the system. The allowed range for the MISO delay will command the required oversampling rate. Effectively, oversampling can work up to a few MHz SCLK.