Questions about LDO design

[devop]

hi everyone:
I have a problem when a design the LDO.can somebody help me.
1,we use the Resr to compensate the loop ,but the ESR is too smill ,maybe 0.1 ~1,why dont we layout a resistance in the chip and use a C without ESR?
2,the esr is too small ,the resistance of pad maybe bigger than it ,how can we use a ESR to compensate??
3,the LDO block is one part of our chip ,but I don,t know the exact value of the C will be load on my block ,and i know the max current maybe 50mA,can someone give a recommended value?

thanks

 

[mists]

LDO question

for question 1, if we use resistor on chip, it will has IR drop issue

 

[corel]

Re: LDO question

I think the ESR 0.1-1 is already big, not small
If add a resistor with capacitor,then will make the ripple bigger

 

[devop]

Re: LDO question

If my ldo block is used to provide power for digital block as the figue ,
question 1:if I layout a resistor at node A and delete ESR(use a c with esr)can cause any problem?
question 2: corel said that the esr maybe very small, the resistance of PAD maybe bigger than that,then the esr=ESR+ Rpad,it must be much bigger ,and cause the ripple to the power,how can i solve the problem??

 

[ee_cchac]

Re: LDO question

The idea is....ldo will usually receive a large current and off chip Cap(*with its esr*), which are all external source provided to LDO to operated.
So, from using point of view, it seems there is no choice for LDO..... somethings external must connect with....

 

[devop]

LDO question

any other opinion??

 

[dhasmana]

LDO question

If you add on chip resistance , PSRR will be degraded and there will be IR drop.If u wanna avoid the IR drop, then u need to add one more pin for the output current which would not be feasible.Also metal resistance (precise) of ~1 Ohm wil take quite a bit of area !

 

[wchenx]

Re: LDO question

The common cap you can buy is always with the esr, usually, for 10µF ceramic cap, the esr could be 10mΩ to 100mΩ.

 

[ameed]

Re: LDO question

hi all,

If you add on chip resistance , PSRR will be degraded and there will be IR drop.If u wanna

avoid the IR drop, then u need to add one more pin for the output current which would not be

feasible.Also metal resistance (precise) of ~1 Ohm will take quite a bit of area :idea:

thanx......

 

[engronger]

Re: LDO question

1:the ESR is not too small. now the LDO i design have a ESR　0.2ohm.
2: i am afraid you can not layout a precise resistor having a so small value. and R on chip has a +/-15% variation
3: the load capacitor is not a importart paramater for our design ,since we need a a ESR because a zero pole is needed . the point associate with ESR and the big Capacitor

hi everyone:
I have a problem when a design the LDO.can somebody help me.
1,we use the Resr to compensate the loop ,but the ESR is too smill ,maybe 0.1 ~1,why dont we layout a resistance in the chip and use a C without ESR?
2,the esr is too small ,the resistance of pad maybe bigger than it ,how can we use a ESR to compensate??
3,the LDO block is one part of our chip ,but I don,t know the exact value of the C will be load on my block ,and i know the max current maybe 50mA,can someone give a recommended value?

thanks

 

[lijianheng]

Re: LDO question

The ESR is not large.