Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question: What's the difference between Borderless SRAM

Status
Not open for further replies.

cpsean

Newbie level 5
Joined
Nov 1, 2003
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
88
Question:
Who can tell me what's the difference
between Borderless SRAM and Bordered SRAM.
especially the layout difference.

Thanks
 

Re: Question: What's the difference between Borderless

Not sure this is the answer but in most SRAM layouts the cell blocks are surrounded by dummy SRAM cells which are not active. These allow for process variations between the dense SRAM cell array and more sparse decoder areas. In processing, the edge of the dense SRAM array, i.e. the edge cells can have different critical dimensions. So to prevent any mis-matching, a dummy cell is added such that edge cells are identical to any other.
Not everyone uses this practise as it is possible to eliminate this processing effect or at least redeuce it considerably and thus the cell array is not bordered with dummy cells.
I have not heard this called bordered or borderless so I may be bordering on the wrong answer.
 

Re: Question: What's the difference between Borderless

I basically catch ur mean, It's called in UMC process
by Memory Compiler of library Vendor
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top