Question about the clock of the FIR pipeline delay

[jony]

fir design

I am designing a fir filter
Is the clock of the fir pipeline delay needs to be at the rate of the sample frequency or or the data frequency?

 

[Renjith]

fir design

Ofcourse, the fir design has to work wrt input sample rate. if ur fir cannot work that speed, then u have to decimate your input samples, at the front end of the fir.

 

[Hero]

Re: fir design

Hi,

Also you can use oversampling technique to reduce input low pass filter requirments.

 

[nashafi]

Re: fir design

I am designing the same thing. How are you taking care of coefficients like
0.000034567
in an HDL language.


Thanks,

-Nauman

 

[echo47]

fir design

Nashafi, are you still stuck on that problem? No luck searching the web?


Maybe your filter design software has a mode for generating integer coefficients instead of floating-point coefficients.