Question about sram control (VHDL)!! thanks!

[vvsvv]

sram vhdl

Now I am doing a project about Video acquisition.
in this project I have to deal with the Video data form the A/D (SAA7111A).
My thought is write "odd field data" to Sram A while read "even field data" from Sram B. and then read "odd field data" from Sram A while write "even field data" from Sram B.

how to program in VHDL?

YOU MAY HELP ME EVEN YOU JUST TELL ME THE RIGHT THOUTHT!!
thank you very much!
:roll:

 

[Husoo]

ram control vhdl

why do u use ram? what for? if the fpga is fast enough to read such a speed like ADC goes then why do u store temporarily samples in ram? just write in and read out. It doesnt make sense to me... or I dont see every detail?

by!

 

[ashishjindal76]

sram vhdl control

what operation u want to do after aqusition. there may be possibility that u may not require ram initially forthat perticular operatin u dont need ram any how u can use one single bit counter. when bit is 1 us can store the data in ram1 and when 0 in ram 2 and u can incriment counter at each clock cycle. also instead of using counter u can use a toggle switch which toggles at every input clock pulse

bye
ashish

 

[vvsvv]

vhdl sram

Ihave to do some math operation after video acquestion.
So I have to store the video data in Sram !

please tell me how to control the CS ,WE, OE of Sram.

May any kind man tell me how to think about the timing of WE,OE ,DATA,ADDRESS?

thank again!

 

[tlp71@hotmail.com]

using vhdl to write sram for common

i think that better is to download the Data Sheet of SRAM whic you would use.
After simply copy the waveform for Read And Write.
is not to hard to make it.

 

[ashishjindal76]

sram delay line control

hi

shall i give u some code in verilog or vhdl for sdram controller which can guide u how to proceed with that. just tell me in which HDL whether verilog or vhdl u want that.

regards
Ashish

 

[vvsvv]

sram vhdl controller

to ashishjindal76:
I will be very appreciate if you give me some reference code in VHDL!!!!!!
^_^

to tlp71@hotmail.com:
I have download the datasheet of sram.
but I dont know how to deal with the timing of
we,oe , data, address.
for example:
how to delay we for 8ns when my cloclk is 13.5Mhz?
thank you again!

Last but not least, thank you alll!!

 

[vvsvv]

sram control

sorry !
I forget give you my email!
Thank you for sharing your code !
my email is

sunhonglin@126.com

thanks again!

 

[tlp71@hotmail.com]

is not necessary to delay really of 8 ns.
The parameters that data sheet say are maximun or minum value to work.
You can go also more slow than the maximum frequency.
To delay some signals you must use a clock and a delay line make whit flip flop.
Bye.
G.

 

[vvsvv]

|----------Twc-------------|
ADDRESS----/---------------------------\---------------
\---------------------------/
/CS___________________________________________/--------
|----Twp------ |
/WE--------------\______________/----------------------
|--Tdw-|Tdh|
DATA---------------------/----------\------
\----------/
Typical min max
TWP--Write Pulse Width 8 ____ 8 ____ 10 ____ ns
tDW-- Data Valid 6 ____ 6 ____ 7 ____ ns
to End of Write
tDH--Data Hold Time 0 ____ 0 ____ 0 ____ ns

tWP Write Pulse Width 8 ____ 8 ____ 10 ____ ns

How to control this sram using VHDL ???
MAY anyone help me with some idea?(or vhdl source code
thank again!!

 

[vvsvv]

the format of SRAM Timing is confused!
but it is right in my notepad.exe!!!!!!!
sorry for that. however
what I plan to use is IDT71V424S of IDT Co.
u may look at the datasheet of it !
thank you again!

 

[tlp71@hotmail.com]

yu may create a counter, and decode some valuse, es for read.

case counter is
when 5 =>
add <= <your add>
cs <= '1';
oe <= '1';
when 10 =>
cs <= '0';
oe <= '0';
add <= <your add>
when 15 =>
data_in<= data_ram;
when 20 =>
cs <= '1';
oe <= '1';
ehrn others =>
"your code"
end case;

this is for example, the numbers are related at you clock frequency.

 

[vvsvv]

to:tlp71@hotmail.com
THANK YOU VERY MUCH!
however, does this code work ?
and do u consider "twp and tdw,tdh " in this source code ?
thanks again?!

 

[tlp71@hotmail.com]

may be, is not complete, you must use VHDL sintax
process()
begin

etc..


using numbers you can find the appropiate timings.

 

[ashishjindal76]

hi

here u can find the vhdl model for sdram controller from Xilinx.

regards
Ashish

 

[ashishjindal76]

now the problem of delay u can solve it using counters and or shift registers that is not a big deal. if u can send me some details of ur project may be i would be in a better position to help u out. just tell me what u need

bye
ashish