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Question about Pullup/Pulldowns

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wereiyou

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In some schematics, pins are both pulled up and down. For example, a pin is pulled up via a 4.7k ohm resistor to 2.5V and is also pulled down via a 1m ohm resistor to ground. Could somebody explain this? I was troubled.:cry:
 

Please give your specific circuit diagram.

nguyennam
 

1MΩ pull-down in the presence of 4.7kΩ pull-up doesn't make sense at all ..

Regards,
IanP
 

wereiyou,
Possibly to prevent static charge build-up between the output and gnd, when the chip is not installed. By the way "m" is the prefix for "milli". Always use upper case M when you mean "Mega".
Regards,
Kral
 

nguyennam said:
Please give your specific circuit diagram.

nguyennam

Part of schematic is shown bleow. The net STP2_VARIANT<2..0> is connected to IO pins of Altera's stratix2.
 

Kral said:
wereiyou,
Possibly to prevent static charge build-up between the output and gnd, when the chip is not installed. By the way "m" is the prefix for "milli". Always use upper case M when you mean "Mega".
Regards,
Kral

Kral:
Could you explain the sentence "Possibly to prevent static charge build-up between the output and gnd, when the chip is not installed. " in detail. I can't catch your meaning.

The pulldown is 1M ohm:|
 

HI
This may not be the case of pullup or pull down.
Here ckt designer may intend to make an potential divider.
 

mohammed.peer said:
HI
This may not be the case of pullup or pull down.
Here ckt designer may intend to make an potential divider.

Why? It seems that the divided voltage is very close to the level of the ground or 2.5V power supply. So I think they can connect this net directly to the ground or the power beacuse there is no difference between these two kinds of connection. Hope for further discussion.:?:
 

he has used the 1M resistor to slightely keep the potential above the gnd....like a floating point......1M is very high resistance.....i dont think it will make any diff by removing it.....unless it is used as potential divider(voltage ref).....
 

I would think the reason for the slight load of the 1M resistor is to keep the signal between the rails. For an input, static buildup could raise the static level above +V or below 0V. For certain inputs this could cause unwanted loads or stresses of the input.

What you see is good design practice related to ESD.

TOK ;)
 

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