Question about pointer to array in VHDL

[mpefareo]

What I was going to do in VHDL is to define a pointer to array, later dereference that pointer to a particular index and assign it to approp variable
I have got this code: The idea is to assign pointer to array of sg_list_t to sg_list_t variable:

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Code VHDL - [expand]
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type sg_list_t is
     record
         va : natural; -- address of buffer, not index in sys_mem
         len : natural; -- length of buffer
    end record;
 
type a_sg_list_t is array(natural range <>) of sg_list_t;
type p_a_sg_list_t is access a_sg_list_t;
 
-- Later in function, I have got
procedure dma_unmap(
     dprop : in dma_prop_t
) is
     alias id : natural is dprop.id;
     variable v_sg_list : sg_list_t; -- this is a variable I was going to assign dereferenced pointer to array
begin
     for i in 0 to pdma(id).sg_table.sg_len - 1 loop
         v_sg_list := pdma(id).p_a_sg_list.all(i);   -- this is the problematic line!!!!!!!!!!!!!!!!!!!!!!!!!
         rm_dma_free(v_sg_list.va);
     end loop;
    rm_table_free(pdma(id).sg_table.sgd_va);
    deallocate(pdma(id).p_a_sg_list);
    pdma(id).dma_state := DMA_OPEN_ST;
end dma_unmap;

---

I have compiled the code with ISIM Xilinx simulator but it complains about v_sg_list := pdma(id).p_a_sg_list.all(i);
There is a way to go around ISIM compilation problem:

---

Code VHDL - [expand]
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procedure dma_unmap(
    dprop               : in dma_prop_t
    ) is
    alias id                : natural is dprop.id;
    variable v_a_sg_list      : a_sg_list_t(0 to dprop.sg_len - 1);
begin
    v_a_sg_list := pdma(id).p_a_sg_list.all;
    for i in 0 to pdma(id).sg_table.sg_len - 1 loop
        rm_dma_free(v_a_sg_list(i).va);
    end loop;
--    rm_table_free(pdma(id).sg_table.sgd_va);
--    deallocate(pdma(id).p_a_sg_list);
--    pdma(id).dma_state := DMA_OPEN_ST;
end dma_unmap;

---

But I don't like this solution.
Has anybody got any ideas of how to sort it?
I'm not sure if it my code or simulator problem ISIM is a bit strange in some cases. I have not tried to use any simulator. Haven't got any
The information in books about VHDL pointers is not good. I could find any examples of similar code in net either.

Has anybody got any ideas is it the code problem, may be it is not posible to do this sort of things in VHDL?

Thank you in advance.

 

[TrickyDicky]

first of all - you havent shown how dma_prop_t is declared. I assume it is a record type as you reference the "id" entry. Is this a pointer, or an integer?
secondly, what is pdma? where is the declaration for this.

without these two things, I cannot say whether what you are doing is correct.

From the looks of it, pdma is an array of records that contain a p_a_sg_list_t. Please show ALL the declarations.

Seconly - please use the code tags in your post to make it easier to read the code!

---------- Post added at 11:25 ---------- Previous post was at 11:24 ----------

In answer to your question about pointers - yes you should be able to do what you are doing. But I need to see all the code to see where you are going wrong.

And just to check - you are aware that none of this is synthesisable correct? I assume this is just a testbench.

 

[FvM]

Before looking into the details of your pointer constructs, a quick question on the way. Do you you understand what you are doing in terms of logic hardware design? I fear, that you are copying concepts from software processors to hardware logic that are effectively non-synthesizable, even if they comply with VHDL syntax rules.

 

[mpefareo]

Sorry for not giving all the information. Sorry about tags,
About coping the stuff from software, yes I do it deliberetlly, supporting 2 ideas is difficult, that is way I decided to copy concept from c to vhdl, and it is only for simulator models nothing else this peace of code was not supposed to be synthesizable. The code is just for testbench.

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Code VHDL - [expand]
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type dma_prop_t is
record
id                      : natural;      -- dma channel id, also index in dma_priv array
dma_len                 : natural;      -- dma length in bytes;
dma_dir                 : dma_dir_t;    -- dma direction
sg_len                  : natural;      -- sg list length
sg_type                 : sg_type_t;    -- sg buffer type
sgt_int_en              : boolean;      -- enable sg table interrupt
sgd_int_en              : boolean;      -- enable sg descriptor interrupt
dma_payload_len_max     : natural;      -- max length for payload
end record;
 
type dma_priv_t is
    record
        id                      : integer;                                  -- dma channel id, also table index in sys_mem array
        dma_dir                 : dma_dir_t;                                -- dma direction
        sg_table                : sg_table_t;                               -- sg_table{ len, {phys_addr(not index), len, descr_addr}}
        p_a_sg_list             : p_a_sg_list_t;                            -- sg_table{ len, {phys_addr(not index), len, descr_addr}}
        dma_len                 : natural;                                  -- dma length in bytes;
        sg_type                 : sg_type_t;                                -- dma buffer type
        sgt_int_en              : boolean;                                  -- enable sg table interrupt
        sgd_int_en              : boolean;                                  -- enable sg descriptor interrupt
        dma_payload_len_max     : natural;                                  -- max length for payload
        dma_state               : dma_state_t;                              -- DMA state
        -- vhdl specific stuff
        dma_control_reg         : std_logic_vector(31 downto 0);            -- dma channel control register
    end record;
 
type adma_priv_t is array(natural range<>) of dma_priv_t;
 
shared variable pdma                   : adma_priv_t(0 to DMA_PORTS - 1);[syntax=vhdl]

---

[/syntax]


Thank you for your help!!!!

 

[TrickyDicky]

Looking at this, there shouldnt be a problem, assuming you have actually created an array and put it into the dma_priv_t you are trying to reference in the problem line.

Pointers can only be created by using the "new" keyword, you cannot create a pointer by referencing something else. You can copy pointers though, but remember about dangling pointers. The following will print out 0 (and is actually a null pointer reference):

process
    type i_ptr is access integer;  
    variable a, b : i_ptr;
  begin
    
    a := new integer;
    a.all := 10;
    b := a;
    DEALLOCATE(a);
    
    echo( Integer'image(b.all) );
    
    wait;
    
  end process;

are you sure you have created the p_a_sg_list element via the "new" construct?

 

[mpefareo]

Thank you for your answer.
Yes I'm doing it in dma_map function

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Code VHDL - [expand]
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p_a_sg_list := new p_a_sg_list_t(0 to pdma(id).sg_table.sg_len - 1);
    for i in 0 to pdma(id).sg_table.sg_len - 1 loop
        p_a_sg_list(i).len := pdma(id).sg_table.sg_desc(i).dma_len;
        p_a_sg_list(i).va  := rm_virt_to_dma(pdma(id).sg_table.sg_desc(i).dma_addr);
    end loop;

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I think it is a problem of ISIM I have noticed it is not very cleaver simulator. Unfortunately I have not got ModelSim.
Thank you very much TrickyDicky!!!

 

[TrickyDicky]

ISIM is fairly new, and not up to speed with the abilities modelsim. Pointers are not used a lot by people and so will be ignored in functionality until people request it or get the bugs fixed. I suggest you raise a support request with Xilinx.

You can get a free edition of modelsim from Altera (but the number of code lines is limited).

Otherwise try GHDL (ive not used it but it's free).

 

[mpefareo]

I have already raised WebCase. Waiting for reply.
ISIM start to irritate a bit, very difficult to do the proper simulation and debuging, it can't be compared to ModelSim functionality.

The design will bee too complicated for using with Free edition of ModelSim.
GHDL has not got Xilinx libraries as far as I know. Like PCIe blocks and others.