shenghuo
Newbie level 4
I met a problem that i cannot solve when i utilize xilinx ISE in my design.
when analyze the top-level design,the error happens with followed information:
No default binding for component: <memory_cntr>. Ports <EN_a,EN_b> do not match.
Please tell me why. I have connected this 2 ports separately to 2 signals,and these 2 signals are also connected to the other ports of submodule.
when analyze the top-level design,the error happens with followed information:
No default binding for component: <memory_cntr>. Ports <EN_a,EN_b> do not match.
Please tell me why. I have connected this 2 ports separately to 2 signals,and these 2 signals are also connected to the other ports of submodule.