kooller
Junior Member level 3
hi everybody,
I have design an AGC based on 3 stage linear dB VGA and peak detector,LPF. and there is DC offset cancel block in the VGA circuit, which is made of a low pass path from the VGA output feedback to the VGA input, so that there will be a zero(about 500Hz) and a pole(about 10khz) in the transfer from the input of VGA to the output in the whole.
But when I am doing the simulation, the problem comes. In my simulation, the input signal is 50khz, The AGC loop will become unstable when the input signal is small(in which case the gain of the VGA and the output resistance of the VGA shold be larger), and the control voltage of the VGA will oscillate. But when the input signal is given larger, the AGC loop will be stable,and work well.
The problem have puzzled me for a few days, and still don't find out how to solve this, can anybody help me. Thank you !
I have design an AGC based on 3 stage linear dB VGA and peak detector,LPF. and there is DC offset cancel block in the VGA circuit, which is made of a low pass path from the VGA output feedback to the VGA input, so that there will be a zero(about 500Hz) and a pole(about 10khz) in the transfer from the input of VGA to the output in the whole.
But when I am doing the simulation, the problem comes. In my simulation, the input signal is 50khz, The AGC loop will become unstable when the input signal is small(in which case the gain of the VGA and the output resistance of the VGA shold be larger), and the control voltage of the VGA will oscillate. But when the input signal is given larger, the AGC loop will be stable,and work well.
The problem have puzzled me for a few days, and still don't find out how to solve this, can anybody help me. Thank you !
