au_sun
Full Member level 2
hi ,
In my ASIC design, after finishing layout i checked for the timing,
the static timing analysis gave a results as follows,
setup slack => 3326 ps,
hold slack => 10 ps,
the target frequency of this design is 40MHZ(ie 25ns time period)
my doubt is that the hold slack margin 10ps is it enough,
else what range of values the hold slack margin should
be obtained in order to get timing safe,
In my ASIC design, after finishing layout i checked for the timing,
the static timing analysis gave a results as follows,
setup slack => 3326 ps,
hold slack => 10 ps,
the target frequency of this design is 40MHZ(ie 25ns time period)
my doubt is that the hold slack margin 10ps is it enough,
else what range of values the hold slack margin should
be obtained in order to get timing safe,