Query on Routing Resources

[ukint]

Hi,
Can anyone enlighten on how the routing resources are decided for each technology?
For eg for 130nm process we go upto 5 metal level whereas for 65nm we go upto 7lm or more. Is there any data to support this?

Thanks,
Ukint

 

[kishore2k4]

My understanding is that the number of metal layers are more or less proportional the logic density the wafers can support. Remember that CMOS processes are driven by digital designs. So if you are using a small process node then you can fit more gates thereby you need more connections so more metal layers. Also with increasing integration(SoC) you need multiple supply rails which will also need more number of metal layers.

The maximum I have heard/read is 9 or 10 for Intel 45nm process.