hornysquid
Newbie level 5
Hello. I am trying to synthesize a module written in SV and get this message despite I checked that signal is being used:
some code:
And apparently, it gets optimized away. What am i doing wrong?
Code:
Warning: Verilog HDL or VHDL warning at crossbar.sv(28): object "next_tx_valid" assigned a value but never read
some code:
Code:
.......
logic next_tx_valid[SLAVES][1:3];
// set round-robin to next non-empty transaction
function logic [$clog2(MASTERS)-1:0] update_rr (input int i);
priority case (1'b1)
next_tx_valid[i][1]: return rr_copy[i]+2'(1);
next_tx_valid[i][2]: return rr_copy[i]+2'(2);
next_tx_valid[i][3]: return rr_copy[i]+2'(3);
default: return rr_copy[i];
endcase // priority case (1'b1)
endfunction
.......
always_ff @(posedge clk) begin
....
// save copy of transaction pointer in case rr_cnt gets
// overwritten in transaction push phase
rr_copy[i] <= rr_cnt[i];
for (int j=1; j<=3; j++) // see next_tx_valid declaration
[SIZE=4][B]next_tx_valid[i][j] <= tx_queue[i][rr_cnt[i]+j].tx_valid;[/B][/SIZE]
end // if (tx.tx_valid)
end // case: READY
WAIT_ACK: begin
if (sif.ack[i]) begin
try[rr_copy[i]][i].ack <= 1'b1;
// if write, then we are done, if read, wait for response
if (tx_queue[i][rr_copy[i]].cmd) begin
sif_state[i] <= READY;
[SIZE=4][B]rr_cnt[i] <= update_rr(i);[/B][/SIZE]
end
else sif_state[i] <= WAIT_RESP;
end // if (sif.ack[i])
end // case: WAIT_ACK
WAIT_RESP: begin
if (sif.resp[i]) begin
try[rr_copy[i]][i].resp <= 1'b1;
try[rr_copy[i]][i].rdata <= sif.rdata[i];
sif_state[i] <= READY;
[SIZE=4][B]rr_cnt[i] <= update_rr(i);[/B][/SIZE]
end // if (sif.resp[i])
end // case: WAIT_RESP
endcase // unique case (sif_state[i])
end // for (int i=0; i<SLAVES; i++)
...............................
end // always_ff @ (posedge clk)
endmodule
And apparently, it gets optimized away. What am i doing wrong?