hanoof190
Newbie level 4
This is a vhdl code in Quartus , I really did everything to solve the problem but I keep got an error.. anyone can helped me
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Code:
library ieee;
use ieee.std_logic_1164.all;
library adk;
use adk.all;
entity mux5_1_1wide is
port (
a_input, b_input,c_input,d_input,e_input: in std_logic;
sel : in std_logic_vector(2 downto 0);
z_out : out std_logic
);
end mux5_1_1wide;
architecture beh of mux5_1_1wide is
component mux21
port ( a0, a1, s0 : in std_logic;
y : out std_logic);
end component;
component inv01
port ( a : in std_logic;
y : out std_logic);
end component;
signal temp0, temp1, temp2, temp3: std_logic;
begin
U1: mux21 port map (a0 => a_input,
a1 => b_input,
s0 => sel(0),
y => temp0);
U2: mux21 port map (a0 => c_input,
a1 => d_input,
s0 => sel(0),
y => temp1);
U3: mux21 port map (a0 => temp0,
a1 => temp1,
s0 => sel(1),
y => temp2);
U4: mux21 port map (a0 => temp2,
a1 => e_input,
s0 => sel(2),
y => temp3);
U5: inv01 port map (a => temp3,
y => z_out);
end beh;
