ashutosh_g
Junior Member level 3
i am new to quartus
i was compiling a basic VQM file of 8 bit adder. I generated the VQM file from
FPGA vision (Synopsys).
i am getting the error message
Error: WYSIWYG LCELL primitive "sum_reg_3_" cannot use datad port when in arithmetic mode
can any one tell me please what does this error message mean ?
i was compiling a basic VQM file of 8 bit adder. I generated the VQM file from
FPGA vision (Synopsys).
i am getting the error message
Error: WYSIWYG LCELL primitive "sum_reg_3_" cannot use datad port when in arithmetic mode
can any one tell me please what does this error message mean ?