[SOLVED] Q about rail to rail OPA with high power supply

[leebluer]

I am working on the rail to rail OPA with high voltage power supply. Considering about HV input voltage, HV MOS are used. While worse matching performance exist for HV MOS, and cause bigger input offset. How to deal with it?

Thanks in advance

 

[FvM]

Is it a question about analog IC design or application of commercially available OP?

 

[leebluer]

Sorry for the unclear, it is about IC design, not for application

 

[dick_freebird]

While your mismatch distribution may be worse, your signal
range should be substantially better (not knowing what you
mean by "high" voltage - I've worked in processes where the
high voltage FET was only 3.6V, and others where the low
voltage FETs were 40V). So your net SNR may be OK, and
determining this (requirements vs capabilities) is a good
place to begin.

If your "natural" capability is going to produce unacceptable
offset voltage then you will have to take circuit measures
such as trimming, chopping, etc. These have their costs and
some systems can't tolerate chopper noise or non-continuous-time
operation.

 

[leebluer]

Finally Vds of input pairs is limited within low voltage level, and LV MOS are used for better match