Puzzled: ISE's FPGA editor and timing analizer have no use?

[Alfred_zhang]

improve timing fpga ise

Hi, thank u for your attention.
I am doing FPGA verification with ISE. The codes are fixed. signals in CDC file will be modified.
Sometimes when the signals in CDC are too many, then after PAR, there will be timing violations. By using timing analizer and FPGA editor, I can find the crital path and located it in the PAR's netlist. But that's all what I can do. To resolve the violation, I will try the whole process again: systhisize->translate->map->PAR. then I may get a good result if I have good luck. If violation again, try the whole process again.

Now u see it's very timing-wasted and a little fool.

U advice wil be appreciated! Or whan's your efficient methods to use FPGA editor and timing analizer?

Thank you!

 

[rberek]

ise fpga editor

Of course those tools have a use, BUT, they do not fix the problems for you, they only point out the problems. In general, here is alot more you can do than just rebuild.

Many, many timing problems are caused by poor HDL coding. Look at the paths that the timing analyzer highlighted and find the associated RTL code. Perhaps you have too much logic between flip flops, perhaps you need to flop the outputs and inputs of your module, etc.

Or, your timing constraints may be incorrect and the tool may be spending alot of effort trying to get signals to time that do need to be timed, or timed as aggressively. For example, signals that cross clock domains. There is no timing relationship between the clock domains, so don't have the timing analyzer try to impose a relationship. I have seen this cause alot of issues on FPGA's that are quite full.

Also, poor placement is a killer too. Having complicated logic that talks to a memory which is halfway across the die from the logic will likely lead to timing issues. Xilinx has tools to improve your logic placement to improve timing.

Finally, trying to cram too much logic on the die, or have it run at too aggressive a clock rate, will lead to issues. The PAR tool will try to fix timing by duplicating logic or using bigger drivers, both of which will add to congestion which can lead to more timing problems if there is little room to place the added logic.

So there are alot of things you can do to try fix the timing other than rerun the tools hoping for a different seed.

If you do efficient code, with well placed logic, and you do still have timing problems, or the RTL code and placement are not easily changed, then it might be time to move up to a bigger FPGA!

Failing all that, than sometimes you do have no recourse but to rebuild several times hoping for better timing.

r.b.

 

[Alfred_zhang]

ise fpga

Thanks rberek.

U have list many possible causes of timing violation which is very comprehensive. But I can't modify the code, whose timng is OK when there is no CDC or only a small CDC. And I will not modify the PAR relust manually. Maybe I can try different synthesize tool and more aggressive timing constraints.

Thanks
Best Regards!

 

[rberek]

timing issues in fpga

Thanks!

I do not have a Xilinx project handy right now, as I've been designing into Altera lately, but there should also be some PAR settings which should allow you to optimize the layout for speed, or area, or a balanced approach (at least there is in Altera, and I can't remember Xilinx's method at the moment). You might find that a different setting may work for you as well.

r.b.

 

[nxtech]

ise fpga

Alfred, most times you dont need to make changes to your code. Are you attempting to use the constraints editor? If not you should.

The constraints editor will allow you to specify various constraints which include logical, physical, and placement. You can control and specify mapping, placement, timing, and synthesis constraints.

You did not indicate what part you are using or what the resource usage is. If you provide that along with the report that ISE generates you may get more input.

Hope this helps.

 

[gbaerf]

Re: Puzzled: ISE's FPGA editor and timing analizer have no u

Hi,

As a tool wise i want to put one point here apart from all the technical discussion happened above
this all simulator xlinx , altera there simulator is mainly build to support there Hardware (FPGA) ....so it will have offcourse less features as compare to stand alone SIM like ModelSIM and ActiveHDL.......

even I know some the cases had the same problem as stated above but that was later solved by the above tools which have some more advanced verification and debbugging features...

with regards,