purpose of using inverter as a sense amplifier at 8T-S SRAM

[parminder]

Hi,
can anyone please tell me that why we are using inverter as a sense amplifier during readout. By using an inverter, we don't get the same voltage of read storage bit i.e inverted output at readout is received. Then why taking output after inverter, why not at rbl node?

Thanks in advance

 

[BradtheRad]

The arrangement of mosfet & invert-gate creates a memory cell. It maintains its state (similar to behavior of an RS flip-flop). Notice the label 'bitline keeper'.

I imagine the other mosfets are turned On and Off to perform read/write operations.

The real circuit may have resistors installed as a network creating a certain amount of hysteresis. I suggest this only because it's not readily obvious what is the range of applied voltage, which causes the invert-gate to change state.

 

[parminder]

i hope you understand that i am talking about the external inverter not cross coupled inverter.

Well suppose bit stored at left side is 0, hence n6 and n5 will be on. The capacitor across read bitline (RBL) will be discharged and hence inverter output start rising from 0 to 1.

Similarly if bit stored at left side = 1, then n6 is OFF. The capacitor across read bitline (RBL) will not be discharged and hence inverter will be 0 always.

the output of inverter is not same as stored bit then how we are reading the stored bit.

 

[BradtheRad]

Your schematic appears to be one element of a static RAM array. A byte consists of a row of 8 such memory cells. Each bit has its read wire in common with a column of other memory cells.

Operation would be more obvious by looking at an entire grid of SRAM byte cells.

To read a byte you apply a voltage simultaneously to a single row, and see whether a high or low appears at each bit sensing column. This is a convenient way to arrange SRAM so that a large number of bytes can be operated by a few wires.

 

[parminder]

@BradtheRad, can you please share the figure of about explanation

 

[dick_freebird]

Your "RBL" -is- the output of the mempry array proper; the
sense amp will be located elsewhere (probably at one end,
the other or both of the read bit lines. The inverter is the
simplest "gain stage" you can make (though with such low
use-quantity, maybe simplicity doesn't matter but standby
current sure does, and inverter may be faster than a (say)
clocked comparator operating current-starved.

If you don't like the inversion, add another. Probably going
to see that anyhow, as your well designed sense amp front
end is not going to be sized to drive off-chip. You need a
few stages of tapered drive gain and enable logic for that.

 

[BradtheRad]

please share the figure of about explanation

Internet search on 'ram array' choosing Images.
You'll see grids of memory cells based on invert-gates or half-bridges.
A few give explanations how static ram works.