Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

puncturer in VHDL or verilog

Thread starter Bob_C
Start date Nov 4, 2009

Status: Not open for further replies.

Nov 4, 2009

#1

B

Bob_C

Member level 2

Hi,

Anyone got code for a puncturer to change a received 1/4 rate to 1/3 rate?

Thanks Bob

Status: Not open for further replies.

Similar threads

I
concatenation in VHDL?
- Started by irfanraina1@123
- Feb 27, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
X
VHDL Testbench (Weird output in the simulation)
- Started by Xenon02
- Jan 21, 2024
- Replies: 18
PLD, SPLD, GAL, CPLD, FPGA Design
M
How do I assign decimal values in verilog?
- Started by mahesh_namboodiri
- Jan 31, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
R
[SOLVED] VHDL code "skip" a line in write procedure
- Started by Raeiu
- Jan 19, 2024
- Replies: 8
PLD, SPLD, GAL, CPLD, FPGA Design
N
Add EMIF IP to VHDL code
- Started by nelky22
- Mar 16, 2024
- Replies: 5
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top