Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There are many systems and circuits to do that. You should provide more info about the pulse characterization.
You can sample the pulse line with 2 FFs in series, and compare their outputs. If the values on the signals is not equal, then you can assume a pulse was detected.
you can detect it with a d-latch or d-flip flop in which the D input is connected to '1' and pulse input is connected to clock pin.with an incomming pulse, output goes high.you can use another FF to reset the first FF and make it ready for another incomming pulse.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
