Propagation delay of Digital PADS in umc 65nm for high speed ADC

[sps101]

Hi,
I am designing a Flash ADC that operates at 1Ghz in umc 65nm. The output of my ADC goes to a frequency divider to divide the frequency to 250Mhz. However, the propagation delay of the PADs is around 3 to 4 ns. I am afraid that the output bits of the ADC through the PADS will get corrupted as each PAD can cause a different amount of propagation delay.
Is there any way to counteract this delay inside the ASIC or outside(on PCB) ?

I have seen several high speed ADC papers where the output bits are at 1Ghz and wonder how those signals don't get corrupted when they traverse through the PADS. Or are there specific PADS which are used for high speed designs?

 

[ThisIsNotSam]

it sounds like you are using digital IOs. they are typically slow. why don't you use an analog IO? a barewire type of IO will do.

at the PCB level, you will face a similar issue to capture signals at a fast rate. depending on your setup, of course.

 

[sps101]

it sounds like you are using digital IOs. they are typically slow. why don't you use an analog IO? a barewire type of IO will do.

at the PCB level, you will face a similar issue to capture signals at a fast rate. depending on your setup, of course.

Thank you for the reply. For the inputs to the ADC I am using analog IO. I thought that since the outputs are digital signals I should use digital pads.Also, the digital pad has a load of only 10fF, so my frequency divider was designed to drive a small load.
So the analog IO pads in the PDK have around 1.5pF load. If I use analog IO for the output, shouldn't my frequency divider be available to drive the load of the external world(PAD load + PCB/Probe load) ?

 

[ThisIsNotSam]

Thank you for the reply. For the inputs to the ADC I am using analog IO. I thought that since the outputs are digital signals I should use digital pads.Also, the digital pad has a load of only 10fF, so my frequency divider was designed to drive a small load.
So the analog IO pads in the PDK have around 1.5pF load. If I use analog IO for the output, shouldn't my frequency divider be available to drive the load of the external world(PAD load + PCB/Probe load) ?

you can use analog IOs to read digital 'signals', that is not an issue

you can also make the frequency divider divide even more, and use a simple digital IO. it will make PCB design/testing simpler. since this is an ADC, you can undersample at the PCB level and still get good measurements.