circuitking
Full Member level 5
Hi, I am reading the paper "24 GHz Stacked Power Amplifier With Optimum Inter-stage Matching Using 0.13 μm CMOS Process". My confusion is how to do the mentioned matching procedure.
Below is the procedure I am followed but I haven't got the required output power.
1.I found Zopt1 for M1 using Loadpull without connecting M2 and M3. Doing loadpull, I got optimum load Zopt1 as 82.015+j45.73 with output power 10.22 dBm(say) (Pin=0 dBm).
2.Next, I took only M2 (No M3 also) (Maintaining the same voltage values around it that would have if it were connected in the full circuit as in the attached figure) and to its source connected a port giving Zopt1 value in it. This time I got it's optimum load impedance Zopt2 as 71.7474+j115.152 with output power 4.05 dBm(say, pout2).
I would like to know whether
1. I am doing it in correct way,
2.Why output power(pout2) is less than pout1.
Thanks
Below is the procedure I am followed but I haven't got the required output power.
1.I found Zopt1 for M1 using Loadpull without connecting M2 and M3. Doing loadpull, I got optimum load Zopt1 as 82.015+j45.73 with output power 10.22 dBm(say) (Pin=0 dBm).
2.Next, I took only M2 (No M3 also) (Maintaining the same voltage values around it that would have if it were connected in the full circuit as in the attached figure) and to its source connected a port giving Zopt1 value in it. This time I got it's optimum load impedance Zopt2 as 71.7474+j115.152 with output power 4.05 dBm(say, pout2).
I would like to know whether
1. I am doing it in correct way,
2.Why output power(pout2) is less than pout1.
Thanks
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