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Problems with 8 bit DDS as it stops "half way"

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dds simulation on modelsim

You've lost me. Please clarify your question.
 

dds change offset

err we know that The vertical scale on the "sine" signal is from -128 to +127:
is there a way that i change shift the whole sine signal like 128 to 255
 

dds xilinix ise

My ModelSim display has a vertical scale of -128 to +127 because I configured ModelSim that way. It wasn't that way by default. If you want to change your vertical scale to something else, use the radix/offset/scale/height settings that I mentioned earlier.
 

Re: DDS Help

see this
 

DDS Help

Do you want to modify the signal in your HDL code (instead of modifying ModelSim's display)? You can do that by multiplying the signal by a scaling factor and than adding an offset constant. For example, to convert from range -128 to +127, to range 128 to 255, you could multiply by 0.5 and then add 192.
 

Re: DDS Help

err i try already but errr offset everything just change the size of the wave
but still i see - and + on my wave
 

DDS Help

Did you remember to change the data bus type or width to accommodate the larger values?
Values from 128 to 255 will overflow an 8-bit signed data bus, and cause false negative values.
 

Re: DDS Help

Hi hope this pdf file which deals with the complete technical details of DDS can help you with your queries.You can find all the relevant terchnical details.
 

Re: DDS Help

Hi this is another pdf file that deals about reconfigurable quadrature oscillator based on direct digital synthesis.This can give u some more insight about scaling the frequency and adjustment of the various quadrature parameters.
 

Re: DDS Help

This is a direcr digital synthesis primer ,a technical overview by analog devices.
 

Re: sine table vhdl dds vhd

echo47 said:
What is the name of the software that's showing you the incorrect waveform?

Can you show us a screen image of the malfunction you see?
Have you configured your waveform viewer to show signed (positive and negative) values?

In your VHDL testbench, where is your "DDS" component? If it's a core, which one did you use, and what parameters did you specify to create it?

Your testbench simulates fine in ModelSim 6.3c. I generated an 8-bit DDS core using Xilinx coregen and "DDS Compiler 2.0". The clock is 500 MHz, the sinewave is 120 MHz. Here's a screen image. The vertical scale on the "sine" signal is from -128 to +127:

How can I make Modelsim view my sine wave as in the quoted message's attachment above?? My sine wave seems just binary numbers
 

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