problem with wait states

[anoop12]

hi all,
I want to insert wait states in a vhdl code which has some read/write operations.
How should I insert them using VHDL? I want to make sure that the code remains
synthesizable.

Thanks in advance
regards

 

[master_picengineer]

Hi anoop12,
Unfortunately, the wait statement is not synthesizable.
Try to find another solution.

 

[arnarendra]

I think you will have to arrive at some condition which will define the wait duration dynamically.
Other way is to delay the signals (flop them as many times as the delay is required) and use.
I might be very premitive but this is what I thought.

 

[master_picengineer]

Yes but I don't recommand this solution. Try to use a counter.

 

[angu]

Hi anoop12,
i think you can insert a wait state, as other states, which are synthesisable.
pls refer the attachment -- this "VHDL reference manual" has proper example (converter) too.