Problem with noise in a highspeed pipeline ADC!

[chency]

pipeline 10b project 0.18

anybody designing a highspeed pipelineADC? I want a discuss with you for the SHA, about bandwidth,open gain,cmfb... do you have interest? thanks

 

[terryssw]

Re: about pipeline ADC!

I have some little experence on pipelined ADCs, may be we can discussed it more? What's your problems?

 

[ywguo]

Re: about pipeline ADC!

Hi,

You may get more help if post concrete problems.


Regards,
Yawei

 

[chency]

Re: about pipeline ADC!

I have some little experence on pipelined ADCs, may be we can discussed it more? What's your problems?

thanks, I used an flip_around SHA in the S/H,but i find the noise and jitter very large ,should I care for the opa or switch or cap in the s/h? a 12b 80Mbps adc.

 

[terryssw]

Re: about pipeline ADC!

For noise, both capacitor and opamp will contribute to the noise. By the ways, how do you simulate the noise? using PSS and then Pnoise simulation?

For jitter, I suppose you means the timing jitter right? since you have only single channel, jitter noise should be not quite large. Is it just traditional filp-around structure using only one capacitor?

A way to reduce timing jitter effect is to make the sampling edge shaper. The shaper the clock transition, the smaller the timing error.

 

[crazyamd]

Re: about pipeline ADC!

For noise, both capacitor and opamp will contribute to the noise. By the ways, how do you simulate the noise? using PSS and then Pnoise simulation?

For jitter, I suppose you means the timing jitter right? since you have only single channel, jitter noise should be not quite large. Is it just traditional filp-around structure using only one capacitor?

A way to reduce timing jitter effect is to make the sampling edge shaper. The shaper the clock transition, the smaller the timing error.

capacitors do not contribute to noise.

 

[terryssw]

Re: about pipeline ADC!

Yes, you are right, capacitor does not contribute to the noise. Only the switches resistance contribute to the thermal noise.

However, In sampled-data systems, It is well known that the total noise power sampled in a capacitor with a switches is equals to kT/C, which is only related to the Capacitance of the sampling cap. So What I said is that the capacitance value affect the amount of noise in the S/H circuits.

 

[chency]

Re: about pipeline ADC!

For noise, both capacitor and opamp will contribute to the noise. By the ways, how do you simulate the noise? using PSS and then Pnoise simulation?

For jitter, I suppose you means the timing jitter right? since you have only single channel, jitter noise should be not quite large. Is it just traditional filp-around structure using only one capacitor?

A way to reduce timing jitter effect is to make the sampling edge shaper. The shaper the clock transition, the smaller the timing error.

thanks again, PSS used to simulate the nois, and the filp-around SHA used two match cap(for a difference input),but i have to care for the SHA's load capacitor of the first stage's, I use a 4 bit ad_da in the first stage. by the way ,how did you divided a pipeline ADC's stage,so as to easy to implement.

 

[terryssw]

Re: about pipeline ADC!

You have 4-bit AD-DA in each stage, so that means you do not use any digital correction?

Also 3.5b stage (closer to your 4-bit) is quite large normally. For high-speed applications usually only 1.5b per stage. However, some research have also so that suitable no. of bit per stage can optimize the power consumption.

For easy to implement, I think 1.5b per stage is easiest since lesser reference voltage, lesser capacitors and switches per stages, and higher the feedback factor of the opamp and thus higher speed. Also 1.5 bit per stage does not have the linearity problem in sub DAC.

 

[chency]

Re: about pipeline ADC!

You have 4-bit AD-DA in each stage, so that means you do not use any digital correction?

Also 3.5b stage (closer to your 4-bit) is quite large normally. For high-speed applications usually only 1.5b per stage. However, some research have also so that suitable no. of bit per stage can optimize the power consumption.

For easy to implement, I think 1.5b per stage is easiest since lesser reference voltage, lesser capacitors and switches per stages, and higher the feedback factor of the opamp and thus higher speed. Also 1.5 bit per stage does not have the linearity problem in sub DAC.

by reason of precision and power dissipation and so on ,I adopt a 4 bit flash sub_ADC followed by 8 1.5_b stages and a final 3-b sub_adc. digital correction also be adopted. I'm also interesting in a 1.5b per stage ADC, last year I finished a 10bit ADC of 1.5b per stage ,but its high power dissipation ,and low convert speed(about 10Mbps) didn't fit my expectation. do you have some paper or thesis about it ? thanks.

 

[terryssw]

Re: about pipeline ADC!

If you want the ADC faster with relative smaller power consumption, I think the most suitable architectures is 1.5b per stage MDAC. Since if you increase the bit per stage you would increase the number of capacitor (the function of DAC) connected to the virtual ground of the opamp in the MDAC, thus decreasing the feedback factor and also the speed dramatically.

Although for 1.5b per stage MDAC many stages must be used, you can scale down the stages to save power and area as the required resolution of the pipelined ADC go down along the pipeline. Also the front-end stage of multi-bit per stage MDAC consume much more power than the front-end stage of 1.5b MDAC for the same performance (due to reduced speed). Probably over 90% of 8-10b pipelined ADC with speed > 40 MS/s using 1.5b per stage structure (You can search some results from the IEEE papers).

One more things is that I don't understand what you means "4 bit flash sub_ADC followed by 8 1.5_b stages and a final 3-b sub_adc" ? Do you means 4b (or should be 3.5b MDAC) for the most front-end and then 1.5b afterwards? How many resolution of your ADC designing?

Can you post more information on the performance of your last designed ADC? technology, supply voltage, power consumption, etc.

 

[chency]

Re: about pipeline ADC!

One more things is that I don't understand what you means "4 bit flash sub_ADC followed by 8 1.5_b stages and a final 3-b sub_adc" ? Do you means 4b (or should be 3.5b MDAC) for the most front-end and then 1.5b afterwards? How many resolution of your ADC designing?

Can you post more information on the performance of your last designed ADC? technology, supply voltage, power consumption, etc.

use the 4b-8x1.5-3b division,though total 14b,but I get rid of the last 2b for the precision 12bit.

my project is a 12bit 80Mbps,with smic .18um mixed cmos proc,3.3v power supply,of cause the less the power consumption is ;the better I need.

 

[terryssw]

Re: about pipeline ADC!

Do you have any reason why do you think 4b front-end stage can save more power? I think it is quite difficult to obtain an 80MS/s front-end stage in 4b per stage, 12 bit precision, since the feedback factor decreased significantly. Also, you need some kind of calibration if you want 12b precision.

 

[pbs681]

Re: about pipeline ADC!

One more things is that I don't understand what you means "4 bit flash sub_ADC followed by 8 1.5_b stages and a final 3-b sub_adc" ? Do you means 4b (or should be 3.5b MDAC) for the most front-end and then 1.5b afterwards? How many resolution of your ADC designing?

Can you post more information on the performance of your last designed ADC? technology, supply voltage, power consumption, etc.

use the 4b-8x1.5-3b division,though total 14b,but I get rid of the last 2b for the precision 12bit.

my project is a 12bit 80Mbps,with smic .18um mixed cmos proc,3.3v power supply,of cause the less the power consumption is ;the better I need.

Hi chency,
I am going to design pipelined ADC by using 0.18 tech. I have few questions(BASIC) regarding the design and don't want to disturb this forum. Can I have your email?
Thanks.

 

[codec]

Re: about pipeline ADC!

Hi,
If your noise level and THD are lower than -80dB, there should be no problem.
Are there any problems in the options of your simulation tool?
I have never used PSS and may be I should try it.

BTW, what is your Cs, unity-gain-bw and power consumption of THA(first SHA)?

 

[sisc1525]

about pipeline ADC!

some books introduce the parameter.razavi's book.

 

[tuza2000]

about pipeline ADC!

i want to design a pipeline adc with 0.18 technology,but i dont know how fast i can design?
i dont want to design high accuracy adc but high speed.
the opamp is the biggest problem,how to design a high speed and high gain opamp with 1.8v supply ?
regards

 

[Btrend]

Re: about pipeline ADC!

Do you have any reason why do you think 4b front-end stage can save more power? I think it is quite difficult to obtain an 80MS/s front-end stage in 4b per stage, 12 bit precision, since the feedback factor decreased significantly. Also, you need some kind of calibration if you want 12b precision.

there are more consideration in using multi-bit as the first stage.
1. it is averageing capacitor, u can apply averaging technique to increase the resolution of first stage without trimming effort. because the first stage is the most important stage in pipeline ADC design. if 4b is used, then the following stage can be released to 8b accuracy only.
2. if 1.5b/per stage is adopted in 12b application, u maybe need 3 high power consuming stage to get the first 4bits, if this is much larger than (1), u have good reasons to use 4b as the first stage.
I had heard that someone use this technique.