ggeorgak
Newbie level 3
I need some help implementing a design from the book " FPGA prototyping by VHDL examples - Xilinx Spartan 3 Version". It should be kind of necessary for someone to consult the book in order to help me out.
I've implemented the fifo buffer circuit and the respective test circuit documented in pages 100-104 including also the pushbutton debouncing circuit.
The problem is that the full led lights up immediately after adding data in the buffer having pressed the write pushbutton although the buffer has a size of 4 elements. I cannot write another vector in the buffer unless I push the read pushbutton which in turn lights up the empty led instantly.
It seems as if my buffer has a size of 1 which cannot be the case. I suspect that pressing the write pushbutton produces a long enough signal that takes up multiple clock cycles effectively filling the buffer with the same value. In turn, pressing the read pushbutton has a similar effect reading all data (which are of the same value) emptying the buffer. But then, why the author has added such a counterintuitive example circuit for testing and implementation on an fpga?
Bit confused, glad if someone could help.
I've implemented the fifo buffer circuit and the respective test circuit documented in pages 100-104 including also the pushbutton debouncing circuit.
The problem is that the full led lights up immediately after adding data in the buffer having pressed the write pushbutton although the buffer has a size of 4 elements. I cannot write another vector in the buffer unless I push the read pushbutton which in turn lights up the empty led instantly.
It seems as if my buffer has a size of 1 which cannot be the case. I suspect that pressing the write pushbutton produces a long enough signal that takes up multiple clock cycles effectively filling the buffer with the same value. In turn, pressing the read pushbutton has a similar effect reading all data (which are of the same value) emptying the buffer. But then, why the author has added such a counterintuitive example circuit for testing and implementation on an fpga?
Bit confused, glad if someone could help.