problem with describing a 4bit ripple counter using verilog

[Vasilis]

verilog ripple counter

I have a problem.Here is a verilog description of a 4 bit ripple counter:

module D_FF(D,Q,CLK,RST);
output Q;
input D,CLK,RST;
reg Q;
always @ (posedge CLK or negedge RST)
if(~RST) Q=1'b0;
else Q=D;
endmodule



module Ripple_Counter(Count,RST,A0,A1,A2,A3);
output A0,A1,A2,A3;
input Count,RST;
reg A0,A1,A2,A3;

D_FF(~A0,A0,Count,RST);
D_FF(~A1,A1,A0,RST);
D_FF(~A2,A2,A1,RST);
D_FF(~A3,A3,A2,RST);

endmodule



module Test_Ripple_Counter;
.
.
.
endmodule

When i try to load the design the following errors appear :
# ERROR: .../simulations/ripleCounter/new.vhd(17): Illegal output port connection (2nd connection).
# Region: /Test_Ripple_Counter/CUT/#D_FF#17
# ERROR: .../simulations/ripleCounter/new.vhd(18): Illegal output port connection (2nd connection).
# Region: /Test_Ripple_Counter/CUT/#D_FF#18
# ERROR: .../simulations/ripleCounter/new.vhd(19): Illegal output port connection (2nd connection).
# Region: /Test_Ripple_Counter/CUT/#D_FF#19
# ERROR:.../simulations/ripleCounter/new.vhd(20): Illegal output port connection (2nd connection).
# Region: /Test_Ripple_Counter/CUT/#D_FF#20
# Error loading design

Does anyone know what's wrong :?:

 

[salma ali bakr]

ripple counter verilog

well, u have two little mistakes:

1-don't make A0,A1,A2,A3 registers
2-put instance name for each D_FF

so it will be like this:
/////////////////////////////////////////////////////////////////////////////////
module Ripple_Counter(Count,RST,A0,A1,A2,A3);
output A0,A1,A2,A3;
input Count,RST;
//reg A0,A1,A2,A3; don't put this line here

//add d0, d1, d2, d3 as instance for each D_FF:

D_FF d0(~A0,A0,Count,RST);
D_FF d1(~A1,A1,A0,RST);
D_FF d2(~A2,A2,A1,RST);
D_FF d3(~A3,A3,A2,RST);

endmodule
////////////////////////////////////////////////////////////////////////////////

it should work now
good luck and feed me back with any other errors

Salma

 

[Vasilis]

ripple counter vhdl

I didn't make A0,A1,A2,A3 registers and now it works fine!
Thanks
Even if you don't add d0,d1,d2,d3 as instance for each d flip flop it's ok.

 

[salma ali bakr]

vhdl code for 4 bit ripple counter

so what was the problem then
it just worked fine by itself later on or what happened???

 

[Vasilis]

ripple counter using verilog

so what was the problem then
it just worked fine by itself later on or what happened???

The problem was the line you told me to remove.
I only modified the code by adding a bus instead of A0,A1,A2,A3 and removed the line with the registers.
here it is:

module Ripple_Counter(Counter,RST,A);
output [3:0]A;
input Counter,RST;

D_FF (~A[0],A[0],Counter,RST);
D_FF (~A[1],A[1],A[0],RST);
D_FF (~A[2],A[2],A[1],RST);
D_FF (~A[3],A[3],A[2],RST);

endmodule

 

[salma ali bakr]

illegal output port connection in verilog

oops....i guess i read ur post quickly...and thought it worked without u making any changes.....i am glad i helped...good luck...

Salma

 

[jay_ec_engg]

4 bit asynchronous counter verilog code

here it worked without any change because outputs will be registered and instance name will be taken by the tool automatically........
But obviously its not a good design practise......