Syukri
Full Member level 5
Track & Hold Circuit
I'm using close loop track and hold circuit...
The circuit use 2 analog buffer before the sample capacitance and after it.
On the analog buffer design firstly I've used ideal current source to trigger the tail current. the value is 100µA.
Then i get dynamic range between 0.04V to 3.221V.
Then in order to fabricate it is put pMOS current source ( as Resistor ) and current mirror circuit. The current source given 100µA so do the current Id for both current mirror nMOS.
But the dynamic range decrase. The top voltage still at 3.22V but the botto one is at 0.3V. This is unacceptable..
Can anyone help me....
p/s: analog buffer architecture is almost like differential amplifier.
I'm using close loop track and hold circuit...
The circuit use 2 analog buffer before the sample capacitance and after it.
On the analog buffer design firstly I've used ideal current source to trigger the tail current. the value is 100µA.
Then i get dynamic range between 0.04V to 3.221V.
Then in order to fabricate it is put pMOS current source ( as Resistor ) and current mirror circuit. The current source given 100µA so do the current Id for both current mirror nMOS.
But the dynamic range decrase. The top voltage still at 3.22V but the botto one is at 0.3V. This is unacceptable..
Can anyone help me....
p/s: analog buffer architecture is almost like differential amplifier.