Zubair Alam
Newbie level 6
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Hi there all,
I am having hard time understanding the parameters for a 32nm technology. Can anyone explain please how,why and what should be the device geometry(gate width,gate length,pitch,height etc)
I am using stanford CNFET model and i want to simulate in 32 nm feature size.
I can varry these parameters:
Lg:gate length,
Lgeff:mean free path,
Lss:gate to source distance,
Ldd:gate to drain distance,
pitch:distance between two CNT,
and please if someone has the mosis/tsmc/intel/ibm micron design rule for 32nm give me the link to it.
Thanks.
I am having hard time understanding the parameters for a 32nm technology. Can anyone explain please how,why and what should be the device geometry(gate width,gate length,pitch,height etc)
I am using stanford CNFET model and i want to simulate in 32 nm feature size.
I can varry these parameters:
Lg:gate length,
Lgeff:mean free path,
Lss:gate to source distance,
Ldd:gate to drain distance,
pitch:distance between two CNT,
and please if someone has the mosis/tsmc/intel/ibm micron design rule for 32nm give me the link to it.
Thanks.
