Problem related to clock skewing and grouping clocks

[ludan]

Hi guys,

I'm trying to solve a problem related to clock skewing.
I've two clocks in my design and I know I can specify to the CTS engine of SOC encounter that I want at most X picoseconds of skew tolerated for that clock. This parameter is called MaxSkew in the .cts specification file. So now let's assume I have clock1 with MaxSkew 300ps and clock2 with MaxSkew 500ps, I want to control the maximum skew between the two domains. I can put clock1 and clock2 below ClkGroup command:
ClkGroup
+ clock1
+ clock2

and encounter will try to have their sink meeting the maximum skew as specified in the clock tree specification file (cfr. the documentation).
Does this mean I cannot specify that I want at most 400ps of skew between my two clock domains?
It looks to me as if encounter is considering all the roots as if they were one :-(

 

[D Saurabh]

Grouping Clocks

If you are putting both the clocks into a ClkGroup that means you want to balance these two clocks. That in turn means you want the clock skew between 2 endpoints within clock1 or between clock1 and clock2 to be as similar as possible. This is what the tool is trying to do here. That is why it appears to u that the tool is considering the 2 roots to be 1. It does not make sense to specify different MaxSkew for the 2 clocks and then put them in the same group. Same grp implies same skew.

 

[raju3295]

Grouping Clocks

yep i agree with saurabh,
U can create two clocks in diff clock groups and specify skew seperatly in the spec file,
if its a sub chip design, u can balance them externally, which will be saving lots of buffer space in the subchip