Problem regarding referencing in Verilog

[haneet]

file is not valid elfclass32 library

Hi Guyz,
I am facing a problem when i am compiling the verilog file attached

Here if u see i have mentioned the $monitor.

when i perform the command
$monitor ("time=%t,PADI_bus_rst=%b",$time,chip.PADI_bus_rst);
then it says:
Elaborating the design hierarchy:
ncelab: *W,MISSYST: Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
If item was defined in a shared-object library, the problem could be:
libvpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS32 library.
libpli.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS32 library..

$monitor ("time=%t,PADI_bus_rst=%b",$time,chip.PADI_bus_rst);
|
ncelab: *E,CUVHNF (./top/tb.v,327|58): Hierarchical name component lookup failed at 'chip'.

and when i do this then no problem:

$monitor ("time=%t,PADI_bus_rst=%b",$time,PADI_bus_rst);

I even checked with the path of the hierarchy if i have given somethng wrong. but that is not the case. The path is also correct.

can any1 help me?

HANEET

 

[haneet]

elfclass32 library

resolved it guyz!!!

it was to do with referencing...
I was referring the design top module with itz module name instead of itz instance name.

haneet

 

[mustangyhz]

Re: elfclass32 library

"referring the design top module with itz module name instead of itz instance name"
what does you mean?