problem in ISE : library modules

[Dylan01]

I am using xilinx ISE tool. In spartan3 library module like AND2,OR2 etc are available. when I used this module and instantiate them , in floorplanner it is showing only input/output buffer. and no other hardware.While when we write some behavioral code like assign c=a&b , in this case floorplanner is showing input/output buffer with a function generator i.e. a look-up table.
In synthesis report also for the AND2 module case the device utilization is 1 AND2 is
Cell Usage :
# BELS : 1
# AND2 : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1

but in second case writing assign
Cell Usage :
# BELS : 1
# LUT2 : 1
# IO Buffers : 3
# IBUF : 2
# OBUF : 1

What is difference here in AND2 and LUT2. does spartan has some special hardware for gates , because it shoud map to some LUT.
I am very confused if i use library module where is its hardware.Implementing higher module like counte with library modules is very less optimized compared to what is inferred.can someone help me at this point

 

[echo47]

The XST synthesizer outputs distinct AND and LUT primitives, however the mapper converts everything to LUTs, so that's what gets routed. Try using FPGA Editor instead of Floorplanner to view the routed chip. You will clearly see the same type LUT in both cases.

I don't know what Floorplanner is doing. I don't get along with that program, so I never use it.

 

[Dylan01]

yes you are right I did it with fpga editor and got the same results. I am also confused what floorplanner was doing.